The present invention relates to a method and circuit for stripping frames from FDDI ring when a frame transmitted to FDDI ring goes round the FDDI ring and thereafter returns to FDDI bridge system transmitted this frames in the FDDI bridge system, and more particularly to an article made to be suitable for a FDDI bridge system using FORMAC+ Am79C830 chip of AMD (Advanced Micro Devices) company for the FDDI ring media access control.
As it is widely known, the FDDI is a high speed network which has a Topology of double ring form, and makes a physical contact by using a fiber optic cable and executes 100 Mbps data rate transmission.
Media access control MAC protocol of FDDI is a timed token passing protocol TTPP.
Above-described TTPP is similar with a release after transmission RAT of token ring MAC protocol (IEEE 802.5) when excluding a point that said TTPP has a limitation of time between tokens received to a certain node.
All of stations connected to the FDDI ring can transmit the frame only in case which captured the token being going round the FDDI ring and enables the frame transmission of other station by transmitting the token on the FDDI ring after completing the frame transmission.
That is, during a station captured the token transmits a frame to the FDDI ring, the other station is in frame receiving state, and the frame transmission is possible by only a station captured a token transmitted by a station finished the frame transmission.
And, the station transmitted the frame has to strip an already transmitted frame returning after having gone round the FDDI ring from the FDDI ring.
FIG. 1 shows a form of data frame of FDDI protocol of general FDDI.
Here, a preamble PA is used for synchronization of the frame with clock of each station and which consists of idles more than sixteen.
And, a starting delimiter SD represents a start of the frame, and a frame control FC represents kinds of the frames, and a destination address DA represents an address of the station wanting the frame to be reached.
And, a source address SA represents an address of the station transmitting the frame, and an information INFO is a data region, and a frame check sequence FCS is a cyclic redundancy check CRC region of 32 bits, and an ending delimiter ED represents an end of the frame excluding a frame status FS region, and the frame status FS represents a frame status after a going round the FDDI ring.
The frame transmitted to the FDDI ring has to be stripped at a station transmitted the frame, and this process is called as a frame stripping, and concretely it is as shown in FIG. 2.
The frame is returned in a NRZI signaling form from a primary in of FDDI and converted in NRZ form through ENDEC: 2-1 and transmitted to FORMAC+: 2--2.
The FORMAC+ (2--2) transmits again this frame to the ENDEC (2-1) and the ENDEC (2-1) converts this again to the NRZI form and transmits to a primary out.
At this moment, when the frame during repeating at present is judged as it a frame already transmitted to my station, this informed to the FORMAC+.
Specifically, a low signal applied to an input pin of an external source address match XSAMAT* which is an external address match signal of the FORMAC+.
When a low signal is inputted to the XSAMAT* pin, the FORMAC+ transmits again to the FDDI ring by inserting an idle symbol to an INFO region of the frame during re-transmitting at present.
This operation is called as a frame stripping.
A frame contained with an idle symbol to the INFO region is called as a fragmentary frame and this is ignored without treating as a normal frame at other station.
And, this fragmentary frame enters the primary in of said station during other station catches a token and thereafter transmits the frame to the FDDI ring, and this is automatically stripped by the FORMAC+.
That is, the frame inputted to a station being in transmitting the frame is automatically stripped by the FORMAC+ without being transmitted again to the FDDI ring.
When showing a frame stripping process entering the frame transmitting process, it will be as FIG. 3.
A method for strpping a frame transmitted to the FDDI ring in a conventional FDDI bridge system using an Am79C830 chip (FORMAC+) of AMD company as a FDDI MAC controller is as follows and its block diagram is as FIG. 4.
The Am79C830 chip includes a receive status pins RS4-0 representing a token coming from the FDDI ring and a receive status of the frame, a transmit status pins XS2-0 representing a token transmitted to the FDDI ring and a transmit status of the frame, a transmit bus X7-0 for transmitting the data to a physical layer device {corresponds to the ENDEC (2-1) of FIG. 2}, and a clock CLK for a synchronization of the FORMAC+ chip operation.
A frame stripping method will be explained by a block diagram of conventional frame stripping circuit shown in FIG. 4.
When the FDDI ring catches a token, the FORMAC+ indicates a token captured state to the receive status pins RS4-0.
When the token captured state is appeared, a control PAL 4-2 becomes to an operation preparing state and the station transmits a frame, and when the frame transmission is finished, a void frame is transmitted at last and a token is transmitted.
A frame transmit status is indicated at the transmit status pins of the FORMAC+ at a time when the station transmits a frame, and in this case, the control PAL 4-2 generates a up signal and increases a coefficient value of a counter 4-3 by 1.
When an already transmitted frame goes round the FDDI ring and returns to the station, a frame receive status is appeared to the receive status pins, and at this time, the control PAL 4-2 generates a down signal and decreases the coefficient value of the counter 4-3 by 1 and generates a generator control signal GCS.
The generator PAL 4--4 generates an external source address match signal XSAMAT+ by synchronizing to a clock synchronization signal when receiving the generator control signal GCS.
This XSAMAT* signal is inputted to the FORMAC+ and the FORMAC+ continues a frame transmission when a present station is in a frame transmitting, that is, the frame is automatically stripped as FIG. 3, and when the FORMAC+ is in a frame transmitting, it is transmitted by containing an idle symbol to an information INFO region of the transmitted frame as FIG. 2.
A frame stripping as this is continued until a coefficient value of the counter becomes to zero 0 or an already transmitted void frame returns.
That is, when the coefficient value of the counter increased upon transmitting the frame at the station is decreased upon receiving the frame and its value becomes to zero, C0 signal is outputted from the counter and this signal is inputted to the control PAL to terminate a generation of a generation control signal so as to make the generator PAL 4--4 not to be able to output any more the external source address match signal whereby the frame stripping is ended.
That is, the control PAL 4-2 stops the operation until a new token is caught from the FDDI ring and then waits.
And, even if the counter coefficient value is not 0, when an already transmitted void frame is returned, this is appeared to the transmit bus X7-0, at this moment, a void frame detect circuit 4-1 senses this and outputs a void frame detect signal VFDS to the control PAL 4-2, and the control PAL 4-2 outputs the GCS signal to the generator PAL 4--4 and strips the void frame during re-transmitting and then waits until the token is captured.
As described above, the conventional frame stripping method is that two kinds of frame counting method and void frame detecting method are used by mixing whereby the frame stripping is ended if one of them is satisfied.
However, in said conventional technique, since the receive status pins and the transmit status pins of the FORMAC+ are asynchronously operated each other (that is, an already transmitted frame can also be received even during a station transmits the frame), there may be a worry of occurring an error operation of the up/down counter which is capable of doing only one operation at one moment, and since a void frame detecting circuit added for supplementing and completing this should be added and provided, it has had a problem of increasing a product cost or increasing of complexity of the circuit.